1 v cc wp scl sda 1 2 3 4 8 7 6 5 a 0 v cc wp scl sda 1 2 3 4 8 7 6 5 a 1 a 2 v ss a 0 a 1 a 2 v ss description the cat24wc66 is a 64k-bit serial cmos eeprom internally organized as 8192 words of 8 bits each. catalysts advanced cmos technology substantially reduces device power requirements. the * catalyst semiconductor is licensed by philips corporation to carry the i 2 c bus protocol. cat24wc66 features a 32-byte page write buffer. the device operates via the i 2 c bus serial interface and is available in 8-pin dip or 8-pin soic packages. pin configuration block diagram pin functions pin name function a0, a1, a2 device address inputs sda serial data/address scl serial clock wp write protect v cc +1.8v to +6v power supply v ss ground cat24wc66 64k-bit i 2 c serial cmos eeprom 400 khz i 2 c bus compatible* 1.8 to 6 volt read and write operation cascadable for up to eight devices 32-byte page write buffer self-timed write cycle with auto-clear schmitt trigger inputs for noise protection features dip package (p, l) soic package (j, k, w, x) ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice doc. no. 1037, rev. h d out ack sense amps shift registers control logic word address buffers start/stop logic state counters slave address comparators 256 x 256 v cc external load column decoders xdec data in storage high voltage/ timing control v ss wp scl a 0 a1 a2 sda 256 256 eeprom h a l o g e n f r e e tm l e a d f r e e commercial, industrial and automotive temperature ranges write protection Ctop 1/4 array protected when wp at v ih 1,000,000 program/erase cycles 100 year data retention 8-pin dip or 8-pin soic packages discontinued part
cat24wc66 2 doc. no. 1037, rev. h absolute maximum ratings* temperature under bias ................. C 55 c to +125 c storage temperature ....................... C 65 c to +150 c voltage on any pin with respect to ground (1) ........... C 2.0v to +v cc + 2.0v v cc with respect to ground ............... C 2.0v to +7.0v package power dissipation capability (t a = 25 c) ................................... 1.0w reliability characteristics d.c. operating characteristics v cc = +1.8v to +6.0v, unless otherwise specified. capacitance t a = 25 c, f = 1.0 mhz, v cc = 5v note: (1) the minimum dc input voltage is C 0.5v. during transitions, inputs may undershoot to C 2.0v for periods of less than 20 ns. maximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc + 2.0v for periods of less than 20ns. (2) output shorted for no more than one second. no more than one output shorted at a time. (3) this parameter is tested initially and after a design or process change that affects the parameter. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from C 1v to v cc +1v. (5) maximum standby current (i sb ) = 10 a for the automotive and extended automotive temperature range. l o b m y sr e t e m a r a pd o h t e m t s e t e c n e r e f e rn i mx a ms t i n u d n e n ) 3 ( e c n a r u d n e3 3 0 1 d o h t e m t s e t , 3 8 8 - d t s - l i m0 0 0 , 0 0 0 , 1e t y b / s e l c y c r d t ) 3 ( n o i t n e t e r a t a d8 0 0 1 d o h t e m t s e t , 3 8 8 - d t s - l i m0 0 1s r a e y p a z v ) 3 ( y t i l i b i t p e c s u s d s e5 1 0 3 d o h t e m t s e t , 3 8 8 - d t s - l i m0 0 0 2s t l o v h t l i ) 4 ( ) 3 ( p u - h c t a l7 1 d r a d n a t s c e d e j0 0 1a m l o b m y sr e t e m a r a ps n o i t i d n o cn i mp y tx a ms t i n u c o / i ) 3 ( e c n a t i c a p a c t u p t u o / t u p n i ) a d s ( v o / i v 0 =8f p c n i ) 3 ( e c n a t i c a p a c t u p n i ) p w , l c s , 2 a , 1 a , 0 a ( v n i v 0 =6f p lead soldering temperature (10 secs) ............ 300 c output short circuit current (2) ........................ 100ma *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tn i mp y tx a ms t i n u i c c t n e r r u c y l p p u s r e w o pf l c s z h k 0 0 1 =3a m i b s ) 5 ( ) v 5 = c c v ( t n e r r u c y b d n a t sv n i v r o d n g = c c 1a i i l t n e r r u c e g a k a e l t u p n iv n i v o t d n g = c c 0 1a i o l t n e r r u c e g a k a e l t u p t u ov t u o v o t d n g = c c 0 1a v l i e g a t l o v w o l t u p n i1 -v c c 3 . 0 xv v h i e g a t l o v h g i h t u p n iv c c 7 . 0 xv c c 5 . 0 +v v 1 l o e g a t l o v w o l t u p t u o v ( c c ) v 0 . 3 + = i l o a m 0 . 3 =4 . 0v v 2 l o e g a t l o v w o l t u p t u o v ( c c ) v 8 . 1 + = i l o a m 5 . 1 =5 . 0v discontinued part
cat24wc66 3 doc. no. 1037, rev. h write cycle limits symbol parameter min typ max units t wr write cycle time 10 ms the write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. during the write cycle, the bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its slave address. a.c. characteristics v cc = +1.8v to +6v, unless otherwise specified output load is 1 ttl gate and 100pf read & write cycle limits power-up timing (1)(2) note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. l o b m y sr e t e m a r a pn i mp y tx a ms t i n u t r u p n o i t a r e p o d a e r o t p u - r e w o p1s m t w u p n o i t a r e p o e t i r w o t p u - r e w o p1s m l o b m y sr e t e m a r a p v 5 . 2 - v 8 . 1v 5 . 5 - v 5 . 4 s t i n u n i mx a mn i mx a m l c s fy c n e u q e r f k c o l c0 0 10 0 4z h k t i ) 1 ( t a t n a t s n o c e m i t n o i s s e r p p u s e s i o n s t u p n i a d s , l c s 0 0 20 0 2s n t a a d n a t u o a t a d a d s o t w o l l c s t u o k c a 5 . 31s t f u b ) 1 ( a e r o f e b e e r f e b t s u m s u b e h t e m i t t r a t s n a c n o i s s i m s n a r t w e n 7 . 42 . 1s t a t s : d h e m i t d l o h n o i t i d n o c t r a t s46 . 0s t w o l d o i r e p w o l k c o l c7 . 42 . 1s t h g i h d o i r e p h g i h k c o l c46 . 0s t a t s : u s a r o f ( e m i t p u t e s n o i t i d n o c t r a t s ) n o i t i d n o c t r a t s d e t a e p e r 7 . 46 . 0s t t a d : d h e m i t d l o h n i a t a d00s n t t a d : u s e m i t p u t e s n i a t a d0 50 5s n t r ) 1 ( e m i t e s i r l c s d n a a d s13 . 0s t f ) 1 ( e m i t l l a f l c s d n a a d s0 0 30 0 3s n t o t s : u s e m i t p u t e s n o i t i d n o c p o t s46 . 0s t h d e m i t d l o h t u o a t a d0 0 10 0 1s n discontinued part
cat24wc66 4 doc. no. 1037, rev. h functional description the cat24wc66 supports the i 2 c bus data transmission protocol. this inter-integrated circuit bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. the transfer is controlled by the master device which generates the serial clock and all start and stop conditions for bus access. the cat24wc66 operates as a slave device. both the master device and slave device can operate as either transmitter or receiver, but the master device controls which mode is activated. pin descriptions scl: serial clock the serial clock input clocks all data transferred into or out of the device. sda: serial data/address the bidirectional serial data/address pin is used to transfer all data into and out of the device. the sda pin is an open drain output and can be wire-ored with other open drain or open collector outputs. a0, a1, a2: device address inputs these pins are hardwired or left unconnected (for hardware compatibility with cat24wc16). when hardwired, up to eight cat24wc66 devices may be addressed on a single bus system (refer to device addressing ). when the pins are left unconnected, the default values are zeros. wp: write protect this input, when tied to gnd, allows write operations to the entire memory. when this pin is tied to vcc, the top 1/4 array of memory is write protected. when left floating, memory is unprotected. figure 3. start/stop timing figure 2. write cycle timing figure 1. bus timing start bit sda stop bit scl t wr stop condition start condition address ack 8th bit byte n scl sda t high scl sda in sda out t low t f t low t r t buf t su:sto t su:dat t hd:dat t hd:sta t su:sta t aa t dh discontinued part
cat24wc66 5 doc. no. 1037, rev. h i 2 c bus protocol the features of the i 2 c bus protocol are defined as follows: (1) data transfer may be initiated only when the bus is not busy. (2) during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock line is high will be interpreted as a start or stop condition. start condition the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the cat24wc66 monitors the sda and scl lines and will not respond until this condition is met. stop condition a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition. device addressing the bus master begins a transmission by sending a start condition. the master sends the address of the particular slave device it is requesting. the four most significant bits of the 8-bit slave address are fixed as 1010 (fig. 5). the next three bits (a2, a1, a0) are the device address bits; up to eight 64k devices may to be connected to the same bus. these bits must compare figure 4. acknowledge timing figure 5. slave address bits acknowledge 1 start scl from master 89 data output from transmitter data output from receiver 1 0100a1a0r/w to the hardwired input pins, a2, a1 and a0. the last bit of the slave address specifies whether a read or write operation is to be performed. when this bit is set to 1, a read operation is selected, and when set to 0, a write operation is selected. after the master sends a start condition and the slave address byte, the cat24wc66 monitors the bus and responds with an acknowledge (on the sda line) when its address matches the transmitted slave address. the cat24wc66 then performs a read or write operation depending on the state of the r/ w bit. acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledg- ing device pulls down the sda line during the ninth clock cycle, signaling that it received the 8 bits of data. the cat24wc66 responds with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8- bit byte. when the cat24wc66 begins a read mode it trans- mits 8 bits of data, releases the sda line, and monitors the line for an acknowledge. once it receives this ac- knowledge, the cat24wc66 will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition. the master must then issue a stop condition to return the cat24wc66 to the standby power mode and place the device in a known state. discontinued part
cat24wc66 6 doc. no. 1037, rev. h a 15 C a 8 slave address s a c k a c k a c k bus activity: master sda line s t a r t a 7 C a 0 byte address data n+31 data a c k s t o p a c k data n a c k p a c k * x xx a 15 C a 8 slave address s a c k a c k data a c k s t o p p bus activity: master sda line s t a r t a 7 C a 0 byte address a c k * x xx write operations byte write in the byte write mode, the master device sends the start condition and the slave address information (with the r/ w bit set to zero) to the slave device. after the slave generates an acknowledge, the master sends two 8-bit address words that are to be written into the address pointers of the cat24wc66. after receiving another acknowledge from the slave, the master device transmits the data to be written into the addressed memory location. the cat24wc66 acknowledges once more and the master generates the stop condition. at this time, the device begins an internal programming cycle to nonvolatile memory. while the cycle is in progress, the device will not respond to any request from the master device. page write the cat24wc66 writes up to 32 bytes of data, in a single write cycle, using the page write operation. the page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the master is allowed to send up to 31 additional bytes. after each byte has been transmitted, cat24wc66 will respond with an acknowledge, and internally increment the five low order address bits by one. the high order bits remain unchanged. if the master transmits more than 32 bytes before sending the stop condition, the address counter wraps around , and previously transmitted data will be overwritten. when all 32 bytes are received, and the stop condition has been sent by the master, the internal programming cycle begins. at this point, all received data is written to the cat24wc66 in a single write cycle. acknowledge polling disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host's write operation, cat24wc66 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if cat24wc66 is still busy with the write operation, no ack will be returned. if cat24wc66 has completed the write operation, an ack will be returned and the host can then proceed with the next read or write operation. write protection the write protection feature allows the user to protect against inadvertent programming of the memory array. if the wp pin is tied to v cc , the top 1/4 of the memory array (locations 1800h to 1fff) is protected and figure 7. page write timing figure 6. byte write timing * = don't care bit for 24wc33 x= don't care bit discontinued part
cat24wc66 7 doc. no. 1037, rev. h scl sda 8th bit stop no ack data out 89 slave address s a c k bus activity: master sda line s t a r t n o a c k data s t o p p becomes read only. the cat24wc66 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device s failure to send an acknowledge after the first byte of data is received. read operations the read operation for the cat24wc66 is initiated in the same manner as the write operation with one excep- tion, that r/ w bit is set to one. three different read operations are possible: immediate/current address read, selective/random read and sequential read. immediate/current address read the cat24wc66 s address counter contains the ad- dress of the last byte accessed, incremented by one. in other words, if the last read or write access was to address n, the read immediately following would ac- cess data from address n+1. if n=e (where e=8191), then the counter will wrap around to address 0 and continue to clock out data. after the cat24wc66 re- ceives its slave address information (with the r/ w bit set to one), it issues an acknowledge, then transmits the 8 bit byte requested. the master device does not send an acknowledge, but will generate a stop condition. selective/random read selective/random read operations allow the master device to select at random any memory location for a read operation. the master device first performs a dummy write operation by sending the start condi- tion, slave address and byte addresses of the location it wishes to read. after cat24wc66 acknowledges, the master device sends the start condition and the slave address again, this time with the r/ w bit set to one. the cat24wc66 then responds with its acknowledge and sends the 8-bit byte requested. the master device does not send an acknowledge but will generate a stop condition. sequential read the sequential read operation can be initiated by either the immediate address read or selective read operations. after the cat24wc66 sends the initial 8-bit byte requested, the master will respond with an ac- knowledge which tells the device it requires more data. the cat24wc66 will continue to output an 8-bit byte for each acknowledge sent by the master. the operation will terminate when the master fails to respond with an acknowledge, thus sending the stop condition. the data being transmitted from cat24wc66 is output- ted sequentially with data from address n followed by data from address n+1. the read operation address counter increments all of the cat24wc66 address bits so that the entire memory array can be read during one operation. if more than e (where e=8191) bytes are read out, the counter will wrap around and continue to clock out data bytes. figure 8. immediate address read timing discontinued part
cat24wc66 8 doc. no. 1037, rev. h figure 9. selective read timing x= don't care bit figure 10. sequential read timing a 15 C a 8 slave address s a c k a c k a c k bus activity: master sda line s t a r t a 7 C a 0 byte address slave address s a c k n o a c k s t a r t data p s t o p xx x bus activity: master sda line data n+x data n a c k a c k data n+1 a c k s t o p n o a c k data n+2 a c k p slave address discontinued part
cat24wc66 9 doc. no. 1037, rev. h ordering information notes: (1) the device used in the above example is a 24wc66ji-1.8te13 (soic, industrial temperature, 1.8 volt to 6 volt operating voltage, tape & reel) (2) product die revision letter is marked on top of the package as a suffix to the production date code (e.g. aywwc). for addit ional information, please contact your catalyst sales office. temperature range blank = commercial (0 ? to 70 ? c) i = industrial (-40 ? to 85 ? c) a e = extended automotive (-40 ? to 125 ? c) = automotive (-40 ? to 105 ? c) prefix device # suffix 24wc66 j i te13 product number tape & reel package p: pdip k: soic (eiaj) j: soic (jedec) l: pdip (lead free, halogen free) w: soic (jedec, lead free, halogen free) x: soic (eiaj, lead free, halogen free) operating voltage blank: 2.5v - 6.0v 1.8: 1.8v - 6.0v -1.8 cat optional company id rev c (2) die revision discontinued part
catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catalyst-semiconductor.com publication #: 1037 revison: h issue date: 03/10/05 copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the company s corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. revision history date rev. reason 3/4/2004 d added commercial temp range in all areas 04/03/04 e update pin configuration update ordering information eliminate data sheet designation 7/22/2004 f added die revision to ordering information 8/3/2004 g update features update dc operating characteristics table & notes 03/10/2005 h update ordering information discontinued part
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